Field of the Invention
The present disclosure generally relates to the field of technology of liquid crystal display, and in particular, to a pixel unit and a method for producing the pixel unit, an array substrate and a display apparatus.
Description of the Related Art
A thin film transistor liquid crystal display (TFT-LCD for short), basically includes an array substrate and an opposite substrate. A space between the array substrate and the opposite substrate is filled with a liquid crystal layer, and the array substrate and the opposite substrate are assembled to form a liquid crystal cell structure.
FIG. 1 is a schematic cross-sectional view showing a pixel unit on an array substrate in the prior art. A plurality of pixel units are distributed on a base substrate 10 of the array substrate. As illustrated in FIG. 1, each of the pixel units includes a thin film transistor (TFT) 20, a pixel electrode 41 and a common electrode 43.
The thin film transistor 20 includes: a gate electrode 21, a gate insulation layer 22 formed on the gate electrode 21, an active layer 23 formed on the gate insulation layer 22, and a source electrode 24 and a drain electrode 25 formed on the active layer 23. Typically, the gate insulation layer 22 is made from materials such as SiOx, SiNx. The pixel electrode 41 and the common electrode 43 are typically made from an ITO material and are separated from each other by a passivation layer 42.
An organic layer 30, as an insulation layer, is provided between the pixel electrode 41 and the drain electrode 25. With the organic insulation layer, it can achieve a better insulation performance than an inorganic insulation layer (typically made from SiNx), and may tend to form a thicker film layer. Generally, the SiNx insulation layer has a thickness of 0.2˜0.6 μm, while the organic insulation layer may have a thickness of up to 2 μm. The greater the thickness of the insulation layer between the drain electrode 25 and the pixel electrode 41 is, the larger the distance between the pixel electrode 41 and the source electrode/drain electrode (24, 25) becomes, the smaller the formed coupling capacitance becomes, and the better the quality of displayed picture becomes.
In order to electrically connecting the pixel electrode 41 with the drain electrode 25 of the thin film transistor, it is desired to form a via hole 50 in the organic insulation layer.
However, as the organic insulation layer has a greater thickness, the via hole 50 has a great depth (up to 2 μm) and a large slope and thus the conductive materials overlapped on a side of the via hole may tend to be broken. In addition, the great depth and poor planarization of the via hole 50 may cause Rubbing Mura phenomenon (i.e., fine stripe-like defects formed on a panel due to an alignment film friction alignment process). Furthermore, so does it when thicker inorganic insulation layer is used.
In order to avoid the above circumstance, a method of directly reducing the slope of the via hole is used in the prior art. FIG. 2 schematically shows a structure of the pixel unit on the array substrate after the slope of the via hole is reduced in the prior art. As shown in FIG. 2, the above problem may be alleviated by regulating the slope of the via hole with process conditions. However, when the depth of the via hole is constant, if the slope of the via hole is reduced, the size of the via hole may be desired to increase, which needs sufficient large size of space at the via hole. In fact, as the pixel units are arranged closely and the via hole has a limited space size, it is very difficult to implement the method of reducing the slope of the via hole.